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Processor-level Selective Replication

Nakka, N., Pattabiraman, K., Iyer, R.
Citation:

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN '07), pp.544,553, 25-28 June 2007.

Visit Publisher Online Entry:
Abstract:

We propose a processor-level technique called selective replication, by which the application can choose where in its application stream and to what degree it requires replication. Recent work on static analysis and fault-injection-based experiments on applications reveals that certain variables in the application are critical to its crash- and hang-free execution. If it can be ensured that only the computation of these variables is error-free, then a high degree of crash/hang coverage can be achieved at a low performance overhead to the application. The selective replication technique provides an ideal platform for validating this claim. The technique is compared against complete duplication as provided in current architecture-level techniques. The results show that with about 59% less overhead than full duplication, selective replication detects 97% of the data errors and 87% of the instruction errors that were covered by full duplication. It also reduces the detection of errors benign to the final outcome of the application by 17.8% as compared to full duplication.

Publication Status:
Published
Publication Type:
Proceedings
Publication Date:
06/25/2007
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