Trustworthy Time-Synchronous Measurement Systems
Today’s power measurement systems operate across multiple interfaces, complex asynchronous communication protocols, and inefficient network topologies that limit their security and prevent their deployment at a wider scale. Sensors, like Phasor Measurement Units (PMU) or fault line detectors, depend on accurate timing across the network. So far that has been realized using the Global Positioning System (GPS) signal. However, using GPS for timing has several disadvantages, not only in cost but also in security. Power measurement systems often establish point-to-point communications, routing information through Ethernet-based data link layers, often using optical fiber. However, the cost of deploying optical cables and the poor scalability of the aforementioned infrastructure do not make it very suitable for wide-area deployment. Other industrial protocols are either centralized solutions, which do not scale and have a single point of failure, or are decentralized scheduling algorithms that do not offer common timing. The solution proposed by this activity is a synchronization and medium access protocol that can operate as a wake-up radio, which complements existing modems used in the grid or can be used as the signaling layer for a radio that exploits power-line communications as well as wireless communications to provide accurate and secure network timing for PMU measurements as well as bounded delay in the data delivery. Our application for the protocol is a cost-effective, resilient, synchronous sensing of the 60Hz power signal, without the need for a GPS receiver. Our design is based on a model used to explain synchronization and coordination in biological networks, called the pulse coupled oscillators model. We call our protocol the Pulse Coupled Synchronization and Scheduling Protocol (PULSESS). We verified the algorithm in simulations, and then designed and implemented a prototype microcontroller implementation followed by a final implementation in a field programmable gate array (FPGA).