Hardware Implementation of Information Flow Signatures Derived via Program Analysis

Dabrowski, P., Healey, W., Pattabiraman, K., Chen, S., Kalbarczyk, Z., Iyer, R.

Workshop on Dependable & Secure Nanocomputing at the Conference on Dependable Systems and Networks (DSN'08), 2008.

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Nanoscale computing devices are on the way to integrating many billions of transistors on a single chip. The implications this has on the complexity of CPU design are enormous: Intel and AMD both have reported well over 100 errata in first revisions of their newest microprocessors, with dozens of these being related to security-sensitive issues. We present an architectural solution that provides trustworthy execution of C code that computes critical data, in spite of potential  hardware and software vulnerabilities. The technique uses both static compiler-based analysis to generate a signature for an application, or operating system, and dynamic hardware/software signature checking. A prototype implementation of the hardware on a soft processor within an FPGA incurs no performance overhead and about 4% chip area overhead, while the software portion of the technique adds between 1% and 69% performance overhead in our test applications, depending on the selection of critical data.

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